TED IC Technique Evaluation and A/D Cell Development.
Abstract
The objectives of this program were to further advance the fabrication technology of small scale GaAs integrated circuits and to demonstrate the technology by fabricating and evaluating a 5 gigasample per second (Gs/sec) analog-to-digital converter bit cell. These objectives were met. In the TED/FET bit cell design the sampling and amplitude quantization are performed by a dual-gate TED under the control of a single-gate TED, the output bit is provided by the dual-gate TED, and the feed forward signal is generated by a FET differential pair. A total of only five active devices, including a FET current source, are required to perform these functions. The sampling rate actually achieved by the A/D cells was in excess of 8 Gs/sec, well beyond the 5 Gs/sec design goal. Additionally, the sampling rate is variable from 0 to 8 Gs/sec, unlike conventional A/D designs which generally operate only at one fixed sample rate, and well below 1 Gs/sec. The chief shortcoming of the A/D bit cells fabricated and tested under this program was inaccuracy of the feed forward gain, which was generally low. This is directly attributable to low FET transconductance, but pointed up the need for a means of adjusting cell gain. Some changes could also be made in the cell layout to improve port-to-port isolation, but this was not a critical item. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1978
- Accession Number
- ADA053320
Entities
People
- Dale C. Claxton
- Ted D. Leisher
- Tom G. Mills