Architecture for Multiple Instruction Stream LSI Processors.

Abstract

Advancements of the semiconductor industry have produced an exponential increase in the capacity of integrated circuit chips. As this trend continues, much more complex systems will be able to be implemented on a single chip. This research is aimed at studying computer architectures which are most suited for LSI implementation. A pipelined multiprocessor architecture is derived and methodology given which determines a layout for such a processor from a given instruction set. The problem of partitioning a processor when it is too large for one chip is also examined. An evaluation of the performance of the pipelined processor as compared to a single stream processor is made. Three program traces are analyzed to study their usage of registers and this data is used to determine the performance of the processors with various degrees of pipelining and number of data registers. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1977
Accession Number
ADA056110

Entities

People

  • William Joseph Kaminsky Jr

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Ground and Sea Platforms
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Circuits
  • Complex Systems
  • Computer Architecture
  • Computer Programming
  • Computers
  • Data Transmission
  • Digital Communications
  • Electrical Engineering
  • Engineering
  • Illinois
  • Instruction Set Architecture
  • Integrated Circuits
  • Large Scale Integration
  • Numerical Analysis
  • Semiconductors
  • Test And Evaluation
  • Universities

Fields of Study

  • Engineering

Readers

  • Economics
  • Parallel and Distributed Computing.

Technology Areas

  • Microelectronics