Complexity Reduction in Galois Logic Design.

Abstract

Two methods of reducing the complexity of the hardware used in Galois logic design are presented: reduced trees of Galois linear modules, and subfield multipliers. The first method lowers the number of modules in a full tree of Galois linear modules and the second method enables multiplication in a Galois field to be done with subfield multipliers. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1977
Accession Number
ADA056190

Entities

People

  • J. M. Marver

Tags

DTIC Thesaurus Topics

  • Air Force
  • Arithmetic
  • Circuits
  • Coefficients
  • Construction
  • Defense Systems
  • Detection
  • Equations
  • Errors
  • Fast Fourier Transforms
  • Image Processing
  • Logic
  • Military Research
  • Numbers
  • Polynomials
  • Prime Numbers
  • Signal Processing

Fields of Study

  • Mathematics

Readers

  • Computer Engineering
  • Riverine Ecology
  • Software Engineering.