Electrical Overstress Test Program and Integrated Circuit Failure Mode Evaluation.

Abstract

This final report describes the SOS diode test structures which will be used for empirical investigation of electrical overstress failure. The test structures, in which important physical parameters are varied, are described in detail and a test plan is presented for the overstress testing that will generate failure data for a sensitivity analysis of pulse power failure level as a function of junction area, epitaxial thickness, junction radius of curvature, doping level and metallization and diffusion spikes. An electrical overstress failure mode and distribution study in integrated circuits is presented. Data on over 1200 devices which were tested on previous programs was analysed to determine failure modes on DTL, RTL, TTL, ECL, MOS and linear integrated circuits. The failure distributions on over 3,000 devices from several different test programs were reviewed to identify 'mavericks.' These 'mavericks' were investigated for distinctive failure modes or unusual preirradiation electrical characteristics. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Apr 26, 1978
Accession Number
ADA059714

Entities

People

  • C. R. Jenkins
  • Dennis R. Alexander
  • R. L. Pease

Organizations

  • Braddock Dunn & McDonald

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuit Analysis
  • Circuits
  • Corporations
  • Electronics
  • Electronics Industry
  • Electronics Laboratories
  • Failure Mode And Effect Analysis
  • Geometry
  • Integrated Circuits
  • Modules (Electronics)
  • P-N Junctions
  • Power Electronics
  • Semiconductor Devices
  • Semiconductors
  • Test And Evaluation
  • Test Equipment
  • Zener Diodes

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Structural Health Monitoring of Composite Structures.