Multimode CPU Design Study.

Abstract

A study was conducted to define a Multimode CPU architecture in which the CPU could handle instruction addressing, data addressing, and data processing. A problem set of signal processing tasks was defined from which the architectural design evolved. The multiplier/FFT interaction was identified as a major architectural constraint. A RALU structure was defined to perform the data addressing and data processing. A microsequence structure was designed to perform the instruction addressing. Two complex-data signal processors were defined and designed at the register level. These processors, along with the Raytheon Micro Signal Processor and the Tracor/RCA General Processing Unit were addressed on their ability to perform benchmarks from the initial problem set. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1978
Accession Number
ADA066241

Entities

People

  • Alexander Mihich
  • Alfred Ess
  • Gary L. Mallaley

Tags

Communities of Interest

  • Advanced Electronics
  • Cyber
  • Energy and Power Technologies
  • Materials and Manufacturing Processes
  • Weapons Technologies

DTIC Thesaurus Topics

  • Accuracy
  • Air Force
  • Algorithms
  • Angle Of Arrival
  • Central Processing Units
  • Computer Programming
  • Computers
  • Crystal Structure
  • Data Processing
  • Decoding
  • Electronic Warfare
  • Integrated Circuits
  • Large Scale Integration
  • Radar
  • Random Variables
  • Signal Processing
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Parallel and Distributed Computing.