Advanced Digital TV System.
Abstract
A laboratory version of a programmable digital processor system for TV bandwidth reduction was designed and placed in operation. The system consists of a TV camera-A/D converter unit, two pipelined microprocessor units, and a frame store-D/A-TV display unit interfaced to a PDP-11/04 minicomputer controller in such a manner that data transfers can be effected between any two units over the PDP-11/04 Unibus under software control of the CPU. The pipelined microprocessor units are software programmable via local program stores which are loaded over the PDP-11/04 Unibus. Each pipelined processor is twelve bits wide and uses three AMD 2901 bit-slice microprocessor chips in conjunction with a 12x12 bit hardware multiplier for high speed computation.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1979
- Accession Number
- ADA072917
Entities
People
- G. Graham Murray
- Philip J. Erdelsky
- Richard V. Keele
- Ronald B. Weiss