Error Correction Coding with NMOS Microprocessors: Concepts. Volume I,

Abstract

Error correction coding can be employed in the design of C3 systems to increase transmission reliability and enhance system effectiveness. The maturation of LSI technology and particularly the ubiquitous microprocessor now allow low-cost simple implementations of error coding hardware. Theoretical fundamentals of linear block codes are reviewed with respect to their suitability to decoder design utilizing 8-bit NMOS microprocessors. Key architectural features of NMOS microprocessors are analyzed to determine those characteristics that are best suited to performing decoding functions. A methodology for evaluating MIL-qualified candidate microprocessors is presented that leads to the selection of a microprocessor for the design of the decoder hardware. (Author)

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1979
Accession Number
ADA072982

Entities

People

  • Eric N. Skoog

Organizations

  • MITRE Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Materials and Manufacturing Processes
  • Space
  • Weapons Technologies

DTIC Thesaurus Topics

  • Air Force
  • Application Software
  • Central Processing Units
  • Charge Coupled Devices
  • Coding
  • Computer Programming
  • Computers
  • Decoding
  • Ions
  • Large Scale Integration
  • Metal Oxide Semiconductors
  • Network Topology
  • Reliability
  • Semiconductors
  • Software Design
  • Standards
  • Test And Evaluation

Readers

  • Computer Programming and Software Development.
  • Parallel and Distributed Computing.

Technology Areas

  • Fully Networked C3
  • Fully Networked C3 - Command and Control