A Regular Layout for Parallel Adders.

Abstract

With VLSI architecture the chip area is a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip in time proportional to log n and with area proportional to n log n. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1979
Accession Number
ADA074455

Entities

People

  • H. T. Kung
  • R. P. Brent

Organizations

  • Carnegie Mellon University

Tags

DTIC Thesaurus Topics

  • Arithmetic
  • Boundaries
  • Capacitance
  • Computations
  • Computer Science
  • Computers
  • Law
  • Mathematics
  • Military Research
  • Pipelines
  • Polynomials
  • Trees (Data Structures)
  • Universities

Readers

  • Electromagnetic Wave Scattering and Antenna Radiation Engineering
  • Integrated Circuit Design and Technology.