Architecture for Higher Level Digital Image Processing.
Abstract
This is the second quarterly status report on a program to investigate various approaches to the design of architecture for higher level digital image processing algorithms being conducted by the Westinghouse Systems Development Division for the Computer Science Center, University of Maryland. This two-year program is a continuation of a program entitled 'Algorithms and Hardware Technology for Image Recognition', which was initiated in 1976. This reports begins with a continuation of a descriptiion of bit slice microprocessors with the emphasis on control units this time, and an examination of commercially available units. Several more Maryland algorithms, namely non-linear probabilistic relaxation, connected components, and Super-link are described. Hardware implementations for non-linear probabilistic relaxation and connected components are described in the next section. The final section shows some tentative conclusions, in light of the above continuing analysis, regarding an appropriate architecture for image processing both for the image processing module and the array of modules.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 30, 1978
- Accession Number
- ADA074851
Entities
People
- Thomas J. Willett
Organizations
- University of Maryland