Shared Resources for Multiple Instruction Stream Pipelined Processors.
Abstract
This research has centered on the performance of functional resources that are used by a single multiple-stream pipelined processor. Such resources include arithmetic functional units and the modules that compose an interleaved memory. The functional requirements of such resources is that they perform some operation and resynchronize their results with the associated stream in the pipelined processor. In some instances, a replicated or pipelined resource can be used to achieve the required performance. However, in this research a simple non-pipelined unit with a fixed cycle time is investigated as a lower cost alternative. This resource is characterized by a cycle time, c, and a deadline, d, which if missed results in a penalty of one non-compute pass through the pipeline. The performance of this type of resource for various resource scheduling techniques has been determined through the use of Markov modeling and some model reduction methods. It is shown that very high performance can be obtained when effective use is made of the available deadlines. An extension to this model allows the consideration of resources with access times not equal to their cycle times. Various applications for this type of resource are examined including an implementation of a cost-effective control store which attains high performance through the use of interleaving.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 1979
- Accession Number
- ADA077150
Entities
People
- Joel Emer
Organizations
- University of Illinois Urbana–Champaign