Test Procedures for Semiconductor Random Access Memories

Abstract

Currently available memory testing algorithms were reviewed and evaluated to assess their inadequacies in testing large scale integrated circuit random access memories (RAMs). Categories of functional faults were proposed to include several types of coupling faults. A neighborhood for pattern sensitive faults was defined. A fault model for stuck-at failures in dynamic RAMs was derived, as were requirements to detect abnormal timing parameters. Procedures to detect the following classes of faults were then developed: (1) Functional faults, (2) neighborhood pattern sensitive faults, (3) stuck-at faults in dynamic RAMs, and (4) abnormal access times.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1979
Accession Number
ADA080450

Entities

People

  • D. S. Suk
  • Sudhakar M. Reddy

Organizations

  • University of Iowa

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Access Time
  • Air Force
  • Algorithms
  • Amplifiers
  • Bipolar Junction Transistors
  • Capacitors
  • Circuits
  • Couplings
  • Electronics Industry
  • Engineering
  • Failure Mode And Effect Analysis
  • Integrated Circuits
  • Large Scale Integrated Circuits
  • Manufacturing
  • Security
  • Semiconductors
  • Two Dimensional

Readers

  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.
  • Integrated Circuit Design and Technology.
  • Theoretical Analysis.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems