Noncoplanar High Power FET.

Abstract

Using a p+ substrate as the gate and employing low-doped V-grooves under the source and drain to reduce parasitic capacitances, a noncoplanar power FET was designed and fabricated which achieved submicron gate lengths with photolithography masks employing a resolution limit of several microns. Device performance was limited by low values of pinch-off voltage and gate breakdown voltage. Ion imlantation or diffusion should enable the breakdown voltage to be raised by virtue of separating the p-n junction from the growth interface.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1979
Accession Number
ADA083682

Entities

People

  • D. M. Collins
  • D. R. Decker
  • J. H. Dully
  • R. D. Fairman
  • S. G. Bandy

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms

DTIC Thesaurus Topics

  • Electrical Properties
  • Electron Beams
  • Electronics Laboratories
  • Electrons
  • Epitaxial Growth
  • Fabrication
  • Field Effect Transistors
  • Frequency
  • Geometry
  • Heat Treatment
  • Ion Implantation
  • Lasers
  • Materials
  • Military Research
  • P-N Junctions
  • Sodium Compounds
  • Transistors

Readers

  • Electrical Engineering
  • Electronics Engineering
  • Nanofabrication and Microfabrication.