Estimation of Confidence Limits for Testing Large Logic Networks.

Abstract

This report describes a methodology and means for accurately determining confidence limits for the reliability of large digital networks, without exhaustively exercising all possible input sequences or simulating all logic faults in the network. The report is divided into two parts. In the first part, some mathematical models to estimate the reliability of digital circuits are presented. A heuristic method of assigning weights to faults depending on their 'importance' in a given circuit is described. The models presented can be used to: (a) predict the reliability of a circuit, (b) evaluate test sequences and (c) develop more accurate reliability models of (redundant) fault tolerant computers. The second part of the report deals with the statistical methods of estimating confidence limits. (Author)

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1980
Accession Number
ADA086281

Entities

People

  • B. Peikari
  • C. H. Kapadia
  • John L. Fike
  • K. Kavipurapu

Organizations

  • Southern Methodist University

Tags

Communities of Interest

  • Advanced Electronics
  • Cyber
  • Energy and Power Technologies
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Computational Science
  • Computers
  • Confidence Limits
  • Data Science
  • Digital Circuits
  • Heuristic Methods
  • Information Science
  • Life Tests
  • Logic
  • Logic Gates
  • Probability
  • Reliability
  • Statistical Analysis
  • Statistics
  • Test And Evaluation
  • Test Equipment
  • Test Methods

Fields of Study

  • Engineering

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Regression Analysis.
  • Theoretical Analysis.