Efficient Multipliers for the FFT,

Abstract

One of the major components in a hardware implementation of the discrete Fourier transform (DFT) is the multiplier hardware. There are algorithms available which reduce the number of multiplication used in computing the DFT, and there are hardware techniques for implementing multipliers. This paper presents an efficient method of using table lookup multipliers for the fat Fourier transform (FFT). This method implements the multipliers with a small number of modest size tables. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jul 15, 1980
Accession Number
ADA090648

Entities

People

  • J. M. Frankovich
  • S. C. Pohlig

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Arithmetic
  • Circuits
  • Computations
  • Data Rate
  • Digital Signal Processing
  • Discrete Fourier Transforms
  • Fast Fourier Transforms
  • Filters
  • Integrals
  • Integrated Circuits
  • Pipelines
  • Signal Processing
  • Standards
  • United States
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Computer Science.
  • Operations Research