Feasibility Study of the Combination of MNOS Elements and Bipolar TTL Peripherals on an LSI Circuit Chip.

Abstract

The objective of this research was to obtain radiation, reliability, and performance data on monolithic test structures containing MNOS memory transistors and n-p-n bipolar transistors. The data indicates that the devices performed acceptably at 100,000 rads (Si). Thin-oxide structures performed satisfactorily after exposure to 500,000 rads(Si). Thus, if these devices were combined into an EAROM memory circuit, a hardness level above 100,000 rads should result. Performance, reliability, and breakdown characteristics were measured and are consistent with parameter values that would be useful for an EAROM.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1980
Accession Number
ADA091952

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