Considerations for an Assembler Scheduled Multi-Microprocessor System.
Abstract
A parallel suitability or processability checker was incorporated into pass one of an INTEL 8080 cross assembler. For an assembler level source program, it yields a suitability factor for parallel processing, a jump structure analysis, and the nodes of Ramamoorthy's Loop Free Program Graph shown on the assembly language program source list. This information can be used to construct the Loop Free Program Graph. Eight assembly language source programs were analyzed to test the suitability checker and investigate favorable characteristics of assembly language loops with respect to parallel processability. Suggestions are made for further development of a parallel task recognizer for assembly language program using Ramamoorthy's connectivity analysis method. Design considerations are outlined for development of an assembler scheduled multi-microprocessor system. The machine would execute source program partitions in parallel on a production basis a large number of times. This would be possible after a combined assembly and schedule of the load modules. Applications envisioned are microprocessor based controllers or instruments that would achieve increased speed at less cost by performing such operations as input, calculations, retrieval, and output simultaneously. Also, economical machines could be designed to study aspects of parallel processing for large scale computers and high level languages.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 26, 1980
- Accession Number
- ADA092216
Entities
People
- Richard Lee Stewart
Organizations
- Air Force Institute of Technology