Self-Diagnosing Design Techniques.
Abstract
A study and analysis of architectures, functional partitioning, and module and component features, required to achieve self-diagnosing microprogrammable capabilities in processors, is described. The results of the self-diagnosing techniques study, which apply to large-scale integrated (LSI) circuits, are summarized in a set of design guidelines. Application of these guidelines to a selected baseline, a digital fly-by-wire aircraft flight control system, has resulted in the design of a self-diagnosing, fault tolerant processor possessing 'failed op(2)' fault tolerance and a probability of failure > 1 x 10 to the -9th power for a two-hour mission. Triplication is employed throughout the design because of the requirement to achieve correct operation after the detection of a second error. Functional, complementary partitioning of the requirements leads to an implementation that can be matched to highly integrated devices. A bit-slice processor implements the application requirements, while the error processing and processor redundancy management is handled by a computer-on-chip (COC) family of devices. Specially designed self-checking checkers and partition interconnections devices provide comprehensive and extended error protection and interlocked reconfiguration control with respect to both consistent and inconsistent errors.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 30, 1978
- Accession Number
- ADA098016
Entities
People
- R. W. Heckelman
- W. W. Knight
- W. W. Straub
Organizations
- General Electric