Introduction to the Configurable Highly Parallel Computer. Revision.

Abstract

The Configurable, Highly Parallel (CHiP) Computer family is introduced. These architectures are built around a lattice of programmable switches and data paths that permit processing elements to be connected in arbitrary patterns. The approach preserves locality. The parameters that determine various family members are discussed including switch configuration storage capacity, switch and processor element degrees and corridor width. An efficient embedding of a complete binary tree is presented to illustrate interconnection pattern programming. An algorithm for solving a system of linear equations is given to illustrate the versatility of configurability. (Author)

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Document Details

Document Type
Technical Report
Publication Date
May 18, 1981
Accession Number
ADA099776

Entities

People

  • Lawrence H Snyder

Organizations

  • Purdue University

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Databases
  • Decomposition
  • Dynamic Programming
  • Electron Beam Lithography
  • Embedding
  • Fabrication
  • Manufacturing
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Trees (Data Structures)

Readers

  • Graph Algorithms and Convex Optimization.
  • Parallel and Distributed Computing.