A Functional Level Preprocessor for Computer Aided Digital Design.
Abstract
While good gate level and register transfer level digital simulators exist, one can not easily integrate the two due to their inherent limitations. A given simulation can not be described partially in gate level and partially in a higher level. A solution is to create a functional level preprocessor and a library of functional device models linked to a gate level simulator's input language. This permits the mixing of behavioral models with gate level models in the same system structure. The combination of processes (element models or primitives) and their structure (interconnections) can be exercised all at one time during a single simulation session. Two separate pieces of software were written to implement a specific solution to the above situation. SISL (Structural Interface to the Salogs Language) was created. This is a functional level preprocessor to SALOGS (SAndia LOGic Simulator) which is an eight-state, MOS, gate level digital systems simulator. SISL will accept functional level systems descriptions and convert them to a form acceptable to SALOGS. The other effort was the building of a functional level modeling library. This library consists of three behavior models: a 4-16 decoder, a 2048 X 8 ROM, and a 256 X 8 RAM. These models are designed to be used in a functional level/gate level model of a digital system and will link to the SALOGS run time system. Together SISL and the modeling library provide the easy use of the top-down approach to digital system design.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1980
- Accession Number
- ADA100784
Entities
People
- Peter G. Raeth
Organizations
- Air Force Institute of Technology