A Preliminary Testability Analysis of the Mil-STD-1862 Architecture.
Abstract
This study has addressed the ramifications of built-in-test (BIT) as an integral part of the military computer family (MCF) architecture. This was done by looking at concurrent and nonconcurrent BIT and how it would fit into the current MCF architecture specifications. The current reporting mechanisms in the MCF architecture were evaluated to see which would best serve as a reporting mechanism for concurrent BIT signals. As an upshot of error detection, an error recovery strategy is proposed. As a consequence of this comprehensive recovery strategy, a set of instructions are proposed that would aid in error recovery. Test and recovery in software is the main thrust of the nonconcurrent BIT section of this study. An error data base is proposed. This data base could be accessed as a history by maintenance personnel to provide information to an intelligent error handler and to provide information for reconfiguration control. Several instructions are proposed for doing fault diagnosis and isolation. Rollback and recovery is discussed along with the concept of a recovery cache. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1981
- Accession Number
- ADA103438
Entities
People
- F. M. Smith
- J. A. Bannister
Organizations
- RTI International