Silicon-on-Sapphire Medium Power MESFET.

Abstract

The key aspect in improving the performance of SOS MESFETs is to reduce the parasitic source resistance. While the extrinsic g sub m of GaAs MESFETs is now close to that of the intrinsic device (i.e., with R sub S = R sub D = 0), SOS MESFETs still have significant progress to be made in the area of source resistance reduction. The source resistance can be most effectively reduced by spacing the gate closer to the n(+) source implant. The smallest spacing is then determined by the gate-to-source breakdown voltage.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 1981
Accession Number
ADA105378

Entities

Organizations

  • Cornell University College of Engineering

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Aluminum
  • Availability
  • Curvature
  • Diffusion
  • Electrical Engineering
  • Electrons
  • Engineering
  • Fabrication
  • Geometry
  • Medium Power
  • Mobility
  • Phosphorus
  • Power
  • Resistance
  • Sapphire
  • Space Charge
  • Universities

Readers

  • Semiconductor Device Technology

Technology Areas

  • Space
  • Space - Space Objects