Processor Displacement: An Area-Time Trade-off Method for VLSI Design.

Abstract

Direct VLSI implementation of pipelined (systolic) processor arrays can lead to an over parallelized design causing the chip to have unused or underutilized area. Processor displacement design is a methodology that provides a spectrum of designs with differing time-area trade offs. The methodology is motivated, presented in detail, and illustrated by several examples. Direct experience for the Transitive Closure and Dynamic Programming systolic arrays is presented. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1982
Accession Number
ADA114706

Entities

People

  • David M. Deruyck
  • John D. Unruh
  • Lawrence H Snyder

Organizations

  • Purdue University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Classification
  • Clustering
  • Computer Programming
  • Computer Science
  • Computers
  • Data Transmission
  • Displacement
  • Dynamic Programming
  • Geometry
  • Judgment
  • Military Research
  • Multiplexing
  • Network Science
  • Pipelines
  • Standards
  • Universities

Fields of Study

  • Engineering

Readers

  • Parallel and Distributed Computing.
  • Structural Dynamics.
  • Systems Analysis and Design