Lateral Seeding of Silicon-on-Insulator.
Abstract
A micro-zone melting growth process using a scanning line-shaped graphite heater has been developed to produce (100) silicon-on-insulator (SOI) material over a three inch wafer. Very low angle grain boundaries (less than 0.3 deg) still exist extensively in the material. A 2 micrometer thick layer of plasma CVD oxide deposited from N20 and SiH4 has been found to be an effective capping structure in preventing the molten silicon from beading up. A SiC coating on the top heating element is used to prevent carbon contamination of the recrystallized film. CMOS devices have been fabricated in the recrystallized SOI material. Surface electron and surface hole mobility values of typically 600 sq cm./V-s and 300 sq cm/V-s, respectively, have been measured. The leakage current is uniformly low, typically in the 10 tro the -13th power A/micrometer channel width range at VDS = 1 V. It has also been determined that the low angle grain boundaries do not have a primary effect on the carrier mobility. Furthermore, the problem of enhanced diffusion of arsenic along the grain boundaries is significant less severe in the present SOI material. The small protrusions found in the surface of the recrystallized film did not contribute to gate shorts in the devices measured. However, they may present a reliability problem. Attempts are underway to improve the process to eliminate the protrusions. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 1982
- Accession Number
- ADA115273
Entities
People
- H. W. Lam
- R. F. Pinizzotto
Organizations
- Texas Instruments