The Configurable, Highly Parallel (CHiP) Approach for Signal Processing Applications.

Abstract

A VLSI design methodology, built around the CHiP architecture, is described. The switch lattice of the CHiP architecture is the primary design abstraction. The lattice is a flexible design medium with constraints that mirror those of raw silicon. An eight point pipelined Fast Fourier Transform design, used as a running example, is of independent interest for its locally connected layout. (Author)

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1982
Accession Number
ADA119116

Entities

People

  • Lawrence H Snyder

Organizations

  • Purdue University

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Aspect Ratio
  • Cell Size
  • Computer Programming
  • Computer Science
  • Computers
  • Digital Signal Processing
  • Embedding
  • Hierarchies
  • Information Systems
  • Language
  • Linear Arrays
  • Military Research
  • Programming Languages
  • Signal Processing
  • Simulations
  • Simulators

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Distributed Systems and Data Platform Development
  • Image Processing and Computer Vision.