Architectures and Algorithms for Parallel Updates of Raster Scan Displays

Abstract

The frame buffer memory organization is the key to achieving high display performance. Traditional frame buffer designs use the scan-line organization which allows several pixels along the length of a scan-line to be updated together. This thesis advocates the symmetric square organization which allows the access of square regions of the display. This organization is based on the belief that the regions of the display which are commonly accessed simultaneously are no more likely to be tall and thin than to be short and wide. The square memory organization is studied for representative display applications and is shown to be indeed better than the scan-line organization. Based on the algorithms for these applications, a display design is presented. This design uses one custom designed LSI chip, 64 copies of which are required to implement the frame buffer memory system.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1981
Accession Number
ADA122104

Entities

People

  • Satish Gupta

Organizations

  • Carnegie Mellon University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Access Time
  • Artificial Intelligence
  • Calligraphic Displays
  • Computer Graphics
  • Computers
  • Display Systems
  • Geometry
  • Gray Scale
  • Host Computers
  • Image Processing
  • Intellectual Property
  • Network Protocols
  • Parallel Computing
  • Shape
  • Shift Registers
  • Two Dimensional
  • Wire

Readers

  • Computer Vision.
  • Human-Computer Interaction (HCI).
  • Parallel and Distributed Computing.