Influence of the Atomic Roughness at the Si-Si-O2 Interface.
Abstract
Special MOS-FET's have been prepared to check a correlation between the atomic roughness at the Si/SiO2 interface (as determined by the novel technique of spot profile analysis in the LEED pattern, SPA-LEED) and the electronic mobility in the MOS-device. The transistors have been tested in the temperature range from room temperature down to liquid helium (4 K). Four different sets of transistors with different roughness have been prepared. The roughness has been determinated at large areas with gate oxide on the same chip (without transistor structures, however). Preliminary measurements of mobility show the predicted correlation between roughness and mobility. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1982
- Accession Number
- ADA122276
Entities
People
- M. Henzler
- P. O. Hahn
Organizations
- Leibniz University Hannover