Design and Implementation of a Single-Chip 1-D Median Filter.

Abstract

The design and implementation of a 1-Dimensional median filter in VLSI is presented. The device is designed to operate an 8-bit sample sequences with a window size of 5 samples. Extensive pipelining and employment of systolic concepts at the bit level enable the chip to filter at rates up to 10 Mega-samples per second. The chip is designed to be implemented with a lambda = 2.5 micro NMOS technology and is 6.2 mm by 5.0 mm in size. A circuit configuration for using the chip in approximate 2-D median filtering is also presented.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1982
Accession Number
ADA123328

Entities

People

  • Kemal Oflazer

Organizations

  • Carnegie Mellon University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Buildings And Structures
  • Circuits
  • Communication Channels
  • Computer Science
  • Employment
  • Filters
  • Filtration
  • Image Processing
  • Logic Gates
  • Networks
  • Order Statistics
  • Research Facilities
  • Sequences
  • Shift Registers
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Regression Analysis.