RAPIDbus Architecture and Realization.

Abstract

RAPIDbus: Architecture and Realization describes a synchronous multiprocessor designed to support sensory processing, image understanding, and control applications. Up to eight board level masters interact with up to eight slaves along a time-multiplexed implementation of a crossbar switch. Two implementations are considered, one based on an Advanced Shottky logic with a bus bandwidth of 16 Mhz and a Versabus host interface. The second implementation, based on an ECL/TTL gate array, permits an estimated 64 Mhz of bus bandwidth and a Versus/Multibus host interface. Segmented memory management a multicast capability between one master and multiple destinations, and a standardized host interface aid in making RAPIDbus an appropriate architecture for robotic applications. (Author)

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1982
Accession Number
ADA126363

Entities

People

  • Arthur C. Sanderson
  • John C. Willis

Organizations

  • Carnegie Mellon University

Tags

Communities of Interest

  • Energy and Power Technologies
  • Ground and Sea Platforms

DTIC Thesaurus Topics

  • Bandwidth
  • Computers
  • Computing System Architectures
  • Crossbar Switches
  • Data Transmission
  • Frequency
  • Local Area Networks
  • Multiprocessors
  • Network Topology
  • Operating Systems
  • Power Supplies
  • Robotics
  • Signal Processing
  • Standards
  • Switches
  • Switching
  • Switching Circuits

Fields of Study

  • Computer science

Readers

  • Computer Networking
  • Integrated Circuit Design and Technology.
  • Positioning, Navigation, and Timing (PNT) Technology.

Technology Areas

  • AI & ML
  • Autonomy
  • Autonomy - Autonomous System Control