Upset Response Testing Of MSI Integrated Circuits.

Abstract

This study developed a standard test method for determining the upset response threshold of MSI integrated circuits. Differences in the upset response of internal logic cells were found that were caused by geometrical differences in the design and layout of internal transistors. An analysis method was developed and incorporated into the test standard which can identify these sensitive locations, providing a basis for selecting operating conditions for upset response testing.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jan 15, 1982
Accession Number
ADA128083

Entities

People

  • Allan H. Johnston

Organizations

  • Boeing

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Space
  • Weapons Technologies

DTIC Thesaurus Topics

  • Accuracy
  • Circuit Analysis
  • Counters
  • Dose Rate
  • Failure Mode And Effect Analysis
  • Ionizing Radiation
  • Logic Gates
  • Measurement
  • Modules (Electronics)
  • Nand Gates
  • Semiconductor Devices
  • Semiconductors
  • Test And Evaluation
  • Test Equipment
  • Test Facilities
  • Test Methods
  • Transistors

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Regression Analysis.