State-of-the-Art Assessment of Testing and Testability of Custom LSI/VLSI Circuits. Volume III. Fault Model Analysis.

Abstract

Physical failure in LSI/VSLI circuits is highly dependent on the fabrication technology being used and result in a very complex faulty behavior. To reduce numbers and types of faults that must be handled for test generating and fault simulation, logic fault models are used. The most popular fault model is the single stuck line (SSL) which can emulate many common physical faults. Non-standard faults like short circuits are more difficult to model-usually require modification to the original circuit to allow use of SSL software. This approach is also ideal for handling Complementary Metal oxide Semiconductors faults. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1982
Accession Number
ADA128651

Entities

People

  • Al J. Carlan
  • M. A. Breuer

Organizations

  • The Aerospace Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Cosmic Rays
  • Digital Circuits
  • Fabrication
  • Failure Mode And Effect Analysis
  • Integrated Circuits
  • Large Scale Integration
  • Logic
  • Logic Gates
  • Manufacturing
  • Nand Gates
  • Semiconductors
  • Short Circuits
  • Test Methods
  • Test Sets
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Computational Modeling and Simulation
  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems