Acoustical Array Processor Design

Abstract

This report describes the design of the acoustical array processor known as the CHI-5. The primary goal of the architecture was to provide hardware efficient, yet economical, in implementing linear predictive coding (LPC) algorithms for analysis and synthesis of speech. The CHI-5 can be used with a host processor or it can be used as a voice terminal in a stand alone data driven mode.

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Document Details

Document Type
Technical Report
Publication Date
Jun 08, 1983
Accession Number
ADA129383

Entities

People

  • Glen J. Culler
  • Michael Mccammon

Organizations

  • CHI Systems (United States)

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Accumulators
  • Addressing
  • Algorithms
  • Circuit Boards
  • Circuits
  • Computational Complexity
  • Computer Programming
  • Computer Programs
  • Computers
  • Data Transmission
  • Decoding
  • Digital Data
  • Instructions
  • Microcode
  • Printed Circuit Boards
  • Printed Circuits
  • Terminals

Readers

  • Robotics and Automation.
  • Speech Processing/Speech Recognition.
  • Systems Analysis and Design