A Systolic Architecture for Singular Value Decomposition,
Abstract
Systolic arrays are highly parallel computing structures specific to particular computing tasks. They are well-suited for reliable and inexpensive implementation using many identical VLSI components. The designs consist of one and two-dimensional lattices of identical processing elements. Communication of data occurs only between neighboring cells. Control signals propagate through the array like data. These characteristics make it feasible to construct very large arrays. Several modern methods in digital signal processing require real time solution of some of the basic problems of linear algebra. Fortunately systolic arrays have been developed for many of these problems. But several gaps remain. Only partially satisfying results have been obtained for the eigenvalue and singular value decompositions, for example. This document considers a systolic array for the singular value decomposition (SVD). In this paper the author discusses two topics. First, he shows how an architecture for computing the eigenvalues of a symmetric matrix can be modified to compute singular values and vectors. Second, he discusses the implementation using VLSI chips of these systolic eigenvalue and SVD arrays.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1983
- Accession Number
- ADA130098
Entities
People
- Robert Schreiber
Organizations
- Stanford University