Optimization Techniques for IC Layout and Compaction,

Abstract

This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1982
Accession Number
ADA132521

Entities

People

  • Gershon Kedem
  • Hiroyuki Watanabe

Organizations

  • University of Rochester

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Computer Programming
  • Computer Science
  • Computers
  • Demographic Cohorts
  • Digital Circuits
  • Evolutionary Algorithms
  • Heuristic Methods
  • Integer Programming
  • Integrated Circuits
  • Linear Programming
  • Mathematical Programming
  • Optimization
  • Symbols
  • Transistors
  • Translations

Fields of Study

  • Computer science

Readers

  • Integrated Circuit Design and Technology.
  • Operations Research