Automated Synthesis of Digital Hardware Modules: Simulation and Verification of Interconnections.

Abstract

The final report describes research in hardware synthesis, layout, compaction and area estimation. The most important results involve the wireability analysis for gate arrays, the derivation of Rent's rule, extensions of Hafer's register-transfer synthesis model, and the specification of a data structure to represent hardware design data for use in an expert system. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1983
Accession Number
ADA135298

Entities

People

  • A. C. Parker

Organizations

  • University of Southern California

Tags

Communities of Interest

  • Human Systems

DTIC Thesaurus Topics

  • Algorithms
  • Computer-Aided Design
  • Computers
  • Electrical Engineering
  • Engineering
  • Expert Systems
  • Integrated Circuits
  • Integrated Systems
  • Language
  • Materials
  • Semiconductors
  • Simulations
  • Specifications
  • Standards
  • Two Dimensional
  • Universities
  • Verification

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Integrated Circuit Design and Technology.
  • Software Engineering.