The Extension and Application of Global Compaction Techniques for Horizontal Scientific Code.

Abstract

This report summarizes the work completed in applying trace scheduling to the Floating Point Systems AP164 array processor. This ongoing project focuses upon trace scheduling. The two main aspects of the proejct are the development of a trace scheduling compiler and to design a single instruction multiple data (SIMD) floating point machine that is optimized for trace scheduling. The aspect of this project which has been done under this ARO grant was the development of a trace scheduler for the AP164 attached processor. This architecture is the most common example of a SIMD machine for which the user writes code. The AP164 offers limited parallelism in that it has three alu's and a limited cross-bar.

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Document Details

Document Type
Technical Report
Publication Date
Nov 08, 1983
Accession Number
ADA135794

Entities

People

  • J. A. Fisher

Organizations

  • Yale University

Tags

DTIC Thesaurus Topics

  • Classification
  • Compilers
  • Computer Science
  • Computers
  • Generators
  • Instructions
  • Language
  • Military Research
  • Numerical Analysis
  • Parallel Processors
  • Scheduling (Production)
  • Security
  • Simulations
  • Universities

Readers

  • Parallel and Distributed Computing.
  • Technical Research and Report Writing.