LSI (Large Scale Integrated) Design for Testability. Final Report of Design, Demonstration, and Testability Analysis.

Abstract

The objective of this effort was to demonstrate IBM Level Sensitive Scan Design methodology as an approach for improving the testability of military LSI/VLSI circuits. LSSD was demonstrated in an LSI component AP101C test bed to be a viable and attractive design approach for military LSI/VLSI components. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1983
Accession Number
ADA135899

Entities

People

  • R. D. Groves
  • R. L. Schoenike

Organizations

  • International Business Machines Corporation (Armonk, NY)

Tags

Communities of Interest

  • C4I
  • Energy and Power Technologies
  • Ground and Sea Platforms

DTIC Thesaurus Topics

  • Central Processing Units
  • Circuit Boards
  • Computer Programming
  • Computer-Aided Design
  • Computers
  • Data Sets
  • Databases
  • Engineering
  • Fabrication
  • Failure Mode And Effect Analysis
  • Floating Point Operations
  • Government Procurement
  • Logic Gates
  • Manufacturing
  • Plastic Explosives
  • Test And Evaluation
  • Test Methods

Readers

  • Integrated Circuit Design and Technology.
  • Software Engineering