A Systolic Design Rule Checker.

Abstract

The authors develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1983
Accession Number
ADA136194

Entities

People

  • R. Kane
  • Sartaj Sahni

Organizations

  • University of Minnesota

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Arrays
  • Automation
  • Computer Science
  • Computers
  • Contracts
  • Fabrication
  • Geometry
  • Image Processing
  • Linear Arrays
  • Machines
  • Mathematics
  • Military Research
  • Minnesota
  • Simulations
  • Universities

Readers

  • Aerodynamics.
  • Electronics Engineering
  • Mathematical Modeling and Probability Theory.

Technology Areas

  • Space