A CRAY-Class Multiprocessor Simulator.

Abstract

A logical-timing instruction-level simulator is described for a hypothetical multiprocessor consisting of CRAY-1's connected to a common memory. It is useful for gaining insight into the design of multiprocessor algorithms and for developing high performance algorithms for CRAY processors with instruction sets similar to the CRAY-1. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1983
Accession Number
ADA136555

Entities

People

  • D. A. Orbits
  • P. M. Summers

Organizations

  • University of Michigan

Tags

DTIC Thesaurus Topics

  • Arithmetic
  • Assembly Languages
  • Central Processing Units
  • Computations
  • Computer Programming
  • Computer Programs
  • Computers
  • Data Rate
  • Engineering
  • Floating Point Operations
  • Information Science
  • Instruction Set Architecture
  • Language
  • Operating Systems
  • Simulations
  • Simulators
  • Systems Engineering

Readers

  • Parallel and Distributed Computing.