VLSI Research, Semi-Annual Technical R&D (Research and Development) Status Report April - October 1983
Abstract
In our architecture research a 41,000 transistor second generation 32 bit processor, which demonstrates the advantages of the reduced instruction set concept, has been successfully fabricated and tested. In addition a 46,000 transistor instruction cache was also found to be fully operational and it incorporated a new redundancy idea that tripled the yield. A new cad tool, a timing verifier called Crystal, was found to be extremely useful as it detected potential performance mistakes during the design process. In the computer aids for design and layout research, 85 copies of the new tools tape have been distributeed to university and industrial labs in the U.S. This tape contains about 25 programs, including several new programs (Lyra, Crystal, Peg and Tpack) . A new improved version of the Waveform-Relaxation based simulator has been developed which utilizes new techniques to speed up convergence and for error control. A new algorithm called BLOSSOM has been developed, which can exploit the parallelism of VLSI for the solution of large-scale linear systems of algebraic equations.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1983
- Accession Number
- ADA138339
Entities
People
- R. W. Brodersen
Organizations
- University of California, Berkeley