The Development and Fabrication of an Implantable, Multiplexed, Semiconductor Multielectrode Array.
Abstract
A new JFET multielectrode array, consisting of a four by four array and sixteen junction field effect transistors, has been fabricated. Changes in the fabrication processes include: The use of three inch wafers, in lieu of one and one quarter inch wafers; positive photoresist, instead of negative photoresist; different impurity sources; different diffusion times and temperatures; and a two metal metallization layer, versus a four metal metallization layer. In addition, two unique NMOS multiplexer circuits have been designed for use with either the JFET multielectrode array, or an NMOS multielectrode array. The first multiplexer circuit contains a count-selectable counter, a one of sixteen output multiplexer, a decoder for generating a sync signal, and sixteen by sixteen multielectrode array, all on a single chip. In addition, the array can be separated from the chip permitting the use of the remaining circuitry with other types and sizes of arrays. The second multiplexer circuit contains the same features of the first multiplexer, plus an additional one of sixteen output multiplexer and a four-bit counter. With this chip, however, the array can not be separated from the remaining circuitry. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1983
- Accession Number
- ADA138788
Entities
People
- R. B. Ballantine
Organizations
- Air Force Institute of Technology