A Circuit Design for Multiplexed Digital Correlation at 60 MHz.

Abstract

Method have recently been developed to improve the speed of digital correlators by application of time division multiplexing techniques. Using one such method, a correlator circuit may be constructed in which several multiplexed correlators are parallel loaded with data in a sequential manner and an overall correlation output is determine by properly sampling the outputs of each mulitplexed correlator. The design of a single 64 x 4 bit mulitplexed correlator is presented. Data selection circuitry to form the correct correlation from several such correlators is described. Design considerations arising from the correlator's desired operational rate of 60 MHz are discussed. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Mar 06, 1984
Accession Number
ADA139117

Entities

People

  • J. H. Layno
  • L. M. Leibowitz

Organizations

  • United States Naval Research Laboratory

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Availability
  • Circuits
  • Classification
  • Clocks
  • Correlators
  • Generators
  • Intervals
  • Logic
  • Logic Gates
  • Military Research
  • Multiplexing
  • Pulse Generators
  • Sampling
  • Security
  • Shift Registers
  • Signal Generators
  • Time Division Multiplexing

Fields of Study

  • Physics

Readers

  • Radio communications and signal processing.
  • Systems Analysis and Design