Implementation of the Sign-Logarithm Arithmetic FFT,

Abstract

The simulation studies described show that sign-logarithm arithmetic can be implemented in a practical digital fast fourier transforms (FFT) analyser. Sign-logarithm arithmetic allows a smaller wordlength than conventional fixed point arithmetic whilst maintaining performance. Discussion of the hardware implementation of such a sign-logarithm FFT shows that power consumption can be less than conventional methods using bipolar multipliers. The use of a smaller wordlength allows a significant simplification of the system into which the FFT is placed and a higher data throughput rate. (Author)

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1983
Accession Number
ADA139355

Entities

People

  • S. J. Kidd

Organizations

  • Royal Signals and Radar Establishment

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Arithmetic
  • Arithmetic Units
  • Computer Simulations
  • Dynamic Range
  • Energy Consumption
  • Intervals
  • Lepidoptera
  • Numbers
  • Real Numbers
  • Self Assembly
  • Sidelobes
  • Signal Processing
  • Simulations
  • Standards
  • Two Dimensional
  • Weighting Functions

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Integrated Circuit Design and Technology.
  • Solar Photovoltaics and Thermoelectric Devices.