Modular Matrix Multiplication on a Linear Array.

Abstract

A matrix-multiplication algorithm on a linear array using an optimal number of processing elements is proposed. The local storage required by the processing elements and the input/output bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading small arrays. The array is well-suited for VLSI implementation. (Author)

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1983
Accession Number
ADA139852

Entities

People

  • I. V. Ramakrishnan
  • P. J. Varman

Organizations

  • University of Maryland

Tags

Communities of Interest

  • C4I

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Arrays
  • Clocks
  • Computations
  • Computer Science
  • Computers
  • Contracts
  • Electrical Engineering
  • Engineering
  • Host Computers
  • Linear Arrays
  • Maryland
  • Mathematics
  • Multiplication Factor
  • Notation
  • Universities

Readers

  • Integrated Circuit Design and Technology.
  • Linear Algebra