On Mapping Homogeneous Graphs on a Linear Array-Processor Model.
Abstract
This paper presents a formal model of linear array processors suitable for VLSI implementation as well as graph representation of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model and the structure of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1983
- Accession Number
- ADA139912
Entities
People
- A. Silberschatz
- D. S. Fussell
- I. V. Ramakrishnan
Organizations
- University of Maryland