Low Power Radiation Hard GaAs RAM
Abstract
The scope of this program is to demonstrate a 1K GaAs static RAM having very low power dissipation, 1 micro W/bit in standby, and a short access time, 10 ns, to meet the requirements of the DARPA Advanced On-Board Signal Processor (AOSP). In the six month period covered by this report the initial processing of the 1K RAM arrays was begun. Testing of several lots revealed a mask error which is currently being corrected. The isolation studies for ultra- low power devices continued with major emphasis on isolation degradation following the Schottky metal process. A theoretical formulation for the leakage behavior of GaAs substrates was initiated, and good agreement between theory and the experimental data was obtained. Upset measurements have been made on a number of 256 bit RAMs using an Am-241 alpha particle source. The numerical value for the failure cross section was found to be similar in magnitude to the area of the Schottky barrier speed-up capacitor, suggesting that the capacitor is primarily responsible for the magnitude of the upset cross section. Single event upset measurements have also been carried out using 40 meV/protons at the NRL cyclotron facility. The results for this case also demonstrated a lower upset cross section for RAMs fabricated without the n(-) layer in the speed-up capacitor. A conceptual design of a new RAM mask set was begun in order to evaluate a wider range of RAM cell configurations. Both 256 and 1K bit arrays are being considered, and emphasis will be placed both on cell designs for enhanced yield and radiation hardness. Enhancement/depletion devices will also be incorporated into the design.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1984
- Accession Number
- ADA139930
Entities
People
- C. G. Kirkpatrick
- R. P. Vahrenkamp