Design Study of Floating Point Systolic VLSI Chip.

Abstract

The objective of this program was to investigate the feasibility of building a floating point processor (24-bit mantissa and 8-bit exponent) on a single ship based on the Hughes Research Laboratories (HRL) present 28-bit fixed point chip (Multiplication Oriented Processor or MOP chip). The plan was to generate any necessary cell logic, layout, or simulations in order to estimate the size of the chip and predict its performance. Since division and square root were not included in the HRL MOP chip, arithmetic algorithms for performing these operations were to be studied. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1984
Accession Number
ADA141868

Entities

People

  • G. R. Nudd
  • J. G. Nash

Organizations

  • HRL Laboratories

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Arithmetic
  • Computations
  • Computer Science
  • Computers
  • Digital Computers
  • Dynamic Range
  • Floating Point Operations
  • Generators
  • Iterations
  • Notation
  • Pipelines
  • Precision
  • Resilience
  • Shift Registers
  • Simulations
  • Square Roots
  • Transistors

Readers

  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.
  • Software Engineering