A Simulation Program with Latency Exploitation for the Transient Analysis of Digital Circuits.

Abstract

This report examines the efficiency that can be obtained in the simulation of large digital integrated circuits with the implementation of latency, that is, inactive gates in a given time interval are bypassed in the simulation. In particular the latency criterion in the program SLATE is studied, and a user's guide to SLATE is included. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1983
Accession Number
ADA142377

Entities

People

  • S. A. Sohail

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Bipolar Junction Transistors
  • Circuit Analysis
  • Circuits
  • Digital Circuits
  • Electrical Engineering
  • Electronic Circuits
  • Electronics Laboratories
  • Fermi Levels
  • Field Effect Transistors
  • Integrated Circuits
  • P-N Junctions
  • Power Electronics
  • Semiconductor Devices
  • Semiconductors
  • Simulations
  • Simulators
  • Transistors

Readers

  • Military Training and Readiness Simulation
  • Systems Analysis and Design
  • Vision Science/Vision Psychology/Cognitive Neuroscience.