Development of Short Gate FET's.

Abstract

The goal of this work was to investigate the performance limit of the standard GaAs FET structure. During the contract period we have constructed an AsC13 epitaxial system used to provide buffer layers for our Fet structures, we have developed a submicron lithographic process using deep U.V. techniques and, using these techniques we have produced working .5 micron gate devices. In addition, we have investigated the 'gettering' of substrates as a technique to improve the mobility of ion implanted layers. The result of this experiment showed a correlation between hall mobilities and gettered substrates. Finally, a investigation of a self aligned source drain structure has commenced and several theoretical studies are reported. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1984
Accession Number
ADA147033

Entities

People

  • G. L. Harris
  • M. G. Spencer
  • R. Haynes

Organizations

  • Howard University

Tags

Communities of Interest

  • Advanced Electronics
  • Ground and Sea Platforms

DTIC Thesaurus Topics

  • Conformal Mapping
  • Crystal Lattice Vibrations
  • Differential Equations
  • Electric Fields
  • Electrical Engineering
  • Electrons
  • Field Effect Transistors
  • High Temperature
  • Measurement
  • Metal-Semiconductor Junctions
  • Plastic Explosives
  • Point Defects
  • Semiconductor Devices
  • Semiconductors
  • Space Charge
  • Temperature Gradients
  • Two Dimensional

Fields of Study

  • Materials science

Readers

  • Semiconductor Device Technology