PNPN Latchup in Bipolar LSI Devices.
Abstract
PNPN latchup was studied both analytically and experimentally in several bipolar LSI technologies including integrated injection logic (I to the second power L), integrated Schottky logic (ISL), Schottky Transistor logic (STL) and emitter coupled logic (ECL). The latchup analysis procedure was expanded and applied to LSI microcircuits representing each of the technologies. This procedure consists of a) the identification of parasitic PNPN paths, b) the electrical characterization of the paths, c) detailed circuit analysis, and d) determination of worst case bias conditions for radiation testing. The identification was performed from chip photomicrographs and composite mask drawings. The characterization was performed experimentally by measuring parasitic transistor gains and SCR parameters on decoupled paths and analytically by using a semiconductor device physics code (PN code) in conjunction with doping profiles. The detailed circuit analysis was performed either by hand or with the circuit analysis code SPICE. Radiation testing was performed at the White Sands Missile Range LINAC facility. The results of the study were, a) latchup cannot occur in non-isolated I to the second power L, b) latchup cannot occur in the internal logic of ISL or STL without causing a problem with electrical performance, c) no latchable paths were found by analysis in the 93471 ECL 4kK RAM, the I/0 buffers on a ISL/STL gate array or the I to the second power L peripherals of the 9408 I to the 3rd power L microprogram sequencer.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1982
- Accession Number
- ADA148775
Entities
People
- Dennis R. Alexander
- R. L. Pease