RAPIDbus: Design of an Extensible Multiprocessor Structure.
Abstract
Research in areas of robotics such as machine vision and control systems can benefit from appropriate increases in the available computational power. If algorithms can be structured to take advantage of task level concurrency, a multiprocessor design can provide cost-effective enhancements to the computational resources while decreasing the impact of subsystem failures. RAPIDbus is described in this report as two evolutionary steps in the development of a system to support research in advanced, integrated, sensor based robotic systems. RAPIDbus I, a four processor architecture, is evaluated based on a two processor implementation fabricated in the laboratory. Building on the first design, RAPIDbus II is described as an extensible, high performance, packet switched structure supporting a multitude of heterogeneous processor-memory nodes. Both RAPIDbus architectures assume a single address space populated by a moderate number of comparatively powerful processors. RAPIDbus II goes beyond the breadth of the earlier architecture by assembling groups of fifteen processors into ensembles called societies. Packet repeaters between societies allow up to sixteen ensembles to be assembled in a problem-dependent configuration within a single shared address space. Although not realized in the current proof-of-concept system, an object layer interface was suggested to maintain cache coherency, support strong data typing, and assist in dynamic memory management.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1984
- Accession Number
- ADA150061
Entities
People
- A. C. Sanderson
- J. C. Willis
Organizations
- Carnegie Mellon University